Flash memories have become more and more popular recently, especially in the area of portable communication devices. The basic structure of a flash memory is similar to that of a MOSFET, including a gate, a drain and a source. Usually a flash memory includes a floating gate and a control gate, as the gate of the MOSFET. In addition, there are some kinds of flash memories with no floating gate, such as a nitride read-only memory (NROM). Differing from other types of flash memory that use a conducting polysilicon or metal floating gate, a nitride read-only memory uses an oxide-nitride-oxide (ONO) layer as a charge-trapping medium. Due to a highly compacted nature of the silicon nitride layer, hot electrons tunneling from the MOS-transistor into the silicon nitride are trapped to form an unequal concentration distribution.
In general, the flash memory has the functions of reading, programming and erasing. When injecting electrons to the floating gate of the memory cell or injecting electrons to the ONO layer of the memory cell, a threshold voltage, at a low voltage initially, of the memory cell increases relatively and results in a current from the drain to the source decreasing. This is the programmed state of the memory cell. While connecting a negative voltage to the control gate, electrons trapped in the floating gate (or trapped in the ONO layer) are removed from the floating gate or the nitride layer to lower the threshold voltage of the memory cell. This is the erased state. Regardless of the state the memory cell is in, it is necessary to operate a reading procedure during which the bit information stored in the memory cell is read.
For reading information stored in a memory cell, two mechanisms are common. In a first mechanism a cell is read by applying predetermined, fixed voltages to the gate and drain input. Its drain/source current is mapped to a memory state by comparing it with a reference current. If the current read is higher than the reference, the cell is determined to be in one logical state (for example a LOW-state). On the other hand, if the current is less than the reference current, the cell is determined to be in the other logical state (for example a HIGH-state). Thus, such a two-state cell stores one bit of digital information.
A second mechanism for sensing the state of a memory cell is to bias the gate of the memory cell with a variable voltage instead of a constant voltage. Here the drain/source current is sensed and compared with a constant current. The gate voltage at which the constant reference current is reached by the measured current indicates the state of the memory cell. For programming and erasing memory cells similar operations are necessary, so called verify operations. Verify operations occur during programming or erasing memory cells, they are reading operations during writing operations that assess a need of a further program or erase pulse in order to properly write the data that is to be written into the cell.
In order to increase memory capacity, flash EEPROM (electrically erasable programmable read only memory) devices are being fabricated with higher and higher density as the state of semiconductor technology advances. Another method for increasing storage capacity is to have each memory cell store more than two states.
For a multi-state or multi-level EEPROM memory cell, the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data. Thus, the information that a given EEPROM array can store, increases with the number of states that each cell can store. EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Pat. No. 5,172,338, which is incorporated herein by reference.
Another known possibility for increasing the storage density is to store more than one bit on a conducting layer, not distinguishing different amounts of electric charge but to store electric charges in different areas of a gate layer. Such a memory cell is known from the above-mentioned nitride read-only memory devices (NROM). From U.S. Patent Publication No. 2002/0118566, which is incorporated herein by reference, it is known how to read two-bit information in nitride read-only memory cells simultaneously. According to the drain-source current of NROM, a logical two-bit combination message can be identified. The observed current is divided into four different zones and each zone represents a specific logical two-bit information, which is LOW and LOW, LOW and HIGH, HIGH and LOW or HIGH and HIGH.
Storing two bits of information in different regions of the nitride layer has the advantage that the difference between the individual states can be detected easier than in a multi-level memory cell. However, the state of the second bit influences the current flowing through the cell when detecting the state of the first bit and vice-versa. This is also referred to as the second bit effect. The described effect is relevant when reading data but also when verifying data during erase or program operations and therefore must be considered when evaluating a detected cell current. Though the second bit effect is small in comparison with the effect caused by the state of the bit to be read, it can become more important as the operational voltage of the memory cell becomes lower. In order to save power and to allow smaller die structures to be used for a semiconductor circuit, the operational voltages of memory modules are getting lower and lower. Whereas 5V and 3.3V were previously used as supply voltages, new devices use voltages of 1.6V for example.
For reading these flash memory cells, it is essential to sense the conduction current across the source and drain electrodes of the cell. Especially for reading of more than two states of a memory cell it is important to have a reference current that exactly reflects the condition of the memory cell. The more states a memory cell is made to store, the more finely divided its threshold window must be. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.
The used reference currents are often generated by reference cells that are in a particular state. In most former single-bit or single-level memory architectures, the reference structure for providing appropriate reference currents has been constituted by an array of four or five flash cells corresponding to a programmed state, an erased state, an over-erased or depletion state and a reading state. These reference cells, once programmed to a predefined level, for example at wafer sort, could not be touched anymore.
For several applications, for example for archiving data, it is important that data can still be correctly read after a long time or large number of writing cycles. In addition, temperature variations are to be considered. These influences affect the currents read from a memory cell. Temperature variations also influence the reference currents. In typical single-level and single-bit devices the margins set to separate the states of a memory cell define big windows for the different states. The windows are big enough to secure that data is correctly read or written under all conditions. In multi-level and multi-bit memories, the windows have been significantly reduced and it has become a problem to ensure a correct functionality under all environmental conditions and over the whole life period. The respective need of more accurate references is illustrated in FIGS. 18, 19 and 20.
The diagram of FIG. 18 relates to a two-state memory cell for storing one bit of data. It shows the voltages and currents in an NROM memory cell. The current ICELL through the memory cell depends on the gate-source-voltage. A lower threshold 121 defines the beginning of an erased state. Below the erased state there is an over-erased state, also called a depletion state. In this state, which is not allowed in normal operation of the memory cell, a current flows from the drain to the source even if no voltage is applied to the gate. The erased and the programmed states are separated by a reference voltage 122. The margin windows for the erased and the programmed state are big enough to fit for all conditions.
FIG. 19 shows that in a multi-level cell the margin windows for all states are reduced. For each of the different states a threshold voltage 121, 123, 124 and 125 is defined. This makes clear that the references 121, 123, 124 and 125 must be more accurate than the references 121 and 122 in the diagram of FIG. 18.
From FIG. 20 it can be seen that in multi-bit memory cells an additional problem arises. When reading the first bit of the memory cell it must be considered that the characteristic depends on the second bit. Without consideration of the second bit effect a logical “1” is detected, when the gate-source voltage is in the range referred to as 126. The range of a logical “0” is referred to as 129. A threshold voltage is referred to as 128. When the second bit effect is considered, a logical “1” is to be detected even if the gate-source voltage is higher than the range 126. The excess range is referred to as 127. Therefore the consideration of the second bit effect further reduces the margin window for detecting the state of the memory cell.
To summarize, there are several effects that require that the reference current or voltage for detecting the logical state of a memory cell are more accurate. This is required not only when first operating the memory device but also over its complete lifetime, when degrading effects change the behavior of the memory cells.
Apart from these specific problems there is a general need for high performance, high capacity and high reliability of non-volatile memory devices. In particular, there is a need to have compact non-volatile memory devices. These compact non-volatile memory devices should have a memory system that minimizes disturbance effects.